array assignment systemverilog

An Introduction to SystemVerilog Arrays

This post of the the first of two which talk about SystemVerilog arrays . In this post, we will talk about static arrays , array assignment , loops and packed vs unpacked arrays .

In SystemVerilog, we can write arrays which have either a fixed number of elements or a variable number of elements.

Fixed size arrays are also known as static arrays in SystemVerilog. When we declare a static array, a fixed amount of memory is allocated to the array at compile time . As a result of this, we can't add new elements or resize the array during simulation.

In contrast, we can allocate extra memory or resize a dynamic array while a simulation is running.

Static arrays are generally simpler to use than dynamic arrays and are similar to verilog arrays . Therefore, we will discuss static arrays in more depth in the rest of this post.

In the next post in this series, we will talk about more advanced SystemVerilog arrays. This includes a discussion of dynamic arrays , queues and associative arrays .

Static Arrays in SystemVerilog

Static arrays are the simplest form of array to work with in SystemVerilog. We use static arrays in exactly the same way as we would use an array in verilog .

The code snippet below shows the general syntax which we use to declare a static array in SystemVerilog.

In this construct, we use the <elements> field to declare how many elements are in our array.

In contrast to verilog, we can use a single number in the <elements> field to determine how many elements are in the array.

When we use this approach, SystemVerilog creates a zero indexed array as this is the most commonly used type of array. This approach is also consistent with the way that arrays in C are declared and created.

However, we can also use the old verilog syntax to specify a value for the low and high indexes in our array. When we use this approach, the <elements> field takes the form [high_index : low_index].

We previously discussed the rest of the fields used in this declaration in the post on SystemVerilog Data Types .

To show how we would declare a SystemVerilog array using both approaches, let's consider a simple example. In this example, we will create an array of 4 bit logic types and we want to have a total of 16 elements.

The SystemVerilog code below shows the two different methods we could use to create this array.

• Array Assignment and Literals

After we have created an array in our SystemVerilog code, we can access individual elements in the array using square brackets.

For example, if we wanted to assign some data to the first element in an array then we would use the syntax shown in the code snippet below.

We use this same syntax to access array elements in verilog.

However, we can also use array literals to assignment data to arrays in SystemVerilog. Array literals provide us with a quick and convenient method to assign values to multiple elements in the array at the same time.

The code snippet below shows the general syntax we use to assign data to an array using an array literal.

We use the <values> field in the above code snippet to assign a value to every element in the array.

We can use three different methods to assign data to the <values> field in this construct. The most common method is to use a comma separated list of values.

The SystemVerilog code below shows how we would assign elements to an array using this technique. We can also simulate this code on eda playground .

In addition to this method, we can also use other techniques to assign the same value to multiple elements in the array.

We actually have two methods which we can use for this. Both of these methods are more concise than writing a comma separated list with duplicated values.

The first approach is to use another pair of curly braces inside the list which shows the value we want to assign. We can then put a number in front of the braces to indicate how many consecutive elements should be assigned this value.

As an example, we might want to create an array and assign all of the elements to 0. The code snippet below shows how we would do this using array literals. This code can also be simulated on eda playground .

In addition to this, we can also use the SystemVerilog default keyword inside our array literal.

We more typically use the default keyword inside of SystemVerilog struct types which we will talk about in a future post.

However, we can also use the default keyword as a convenient way to assign the same value to every element in a static array. We can't use this technique with dynamic arrays though.

As an example, we might want to create an array and assign all of the elements to 0. The code snippet below shows how we would do this using the default keyword. We can also simulate this code on eda playground .

When we work with arrays in SystemVerilog it is possible that we may try to assign data to an array element which is out of bounds . When we are working with static arrays, any attempt to do this is simply ignored.

Array Loops

When we work with arrays in any programming language, one common operation is iterating over every element in the array.

There are actually two different methods which we can use to do this in SystemVerilog.

In both case, we make use of a SystemVerilog loops . There are several types of loop which we can use in SystemVerilog and we discuss this in more detail in a later post.

However, let's take a look at both of the methods we can use to iterate over an array in more detail.

• The for loop

The first method makes use of the SystemVerilog for loop which we discuss in more depth in a later post.

The code snippet below shows the general syntax which we use to implement a for loop in SystemVerilog. This syntax is exactly the same as we use in verilog for loops .

We use the <initial_condition> field to set the initial value of our loop variable .

The <stop_condition> field is a conditional statement which determines how many times the loop runs. The for loop will continue to execute until this field evaluates as false.

The <increment> field determines how the loop variable is updated in every iteration of the loop.

We can use the for loop to generate the index for every element in an array. We can then use the loop variable to access each of the elements in the array in turn.

The code snippet below shows how we would do this in SystemVerilog. This example can also be simulated on eda playground .

In this example, we initialize the loop variable (i) to 0 in order to get the lower index of the array. We then use the $size macro to get the index of the final element in our array.

The $size macro is a built in function in SystemVerilog which returns the number of elements in an array.

Finally, we use the SystemVerilog increment operator to increment the value of the loop variable by one on every iteration. As we can see for this example, we can use C style increment and decrement operators in our SystemVerilog code.

From this we can see how the loop variable i is increased fro 0 to 7 in the for loop. This allows us to access each of the array elements in turn by using the loop variable as an index.

• The foreach Loop

The second method which we can use to loop over an array in SystemVerilog is the foreach loop.

This is a new type of loop which was introduced as a part of the SystemVerilog language. The foreach loop is designed to provide a more concise way of looping over an array.

The code snippet below shows the general syntax for the foreach loop.

In this construct, we use the <array_name> field is select the array which we want to loop over.

The <iterator> field is then automatically incremented from the low index to the high index of the selected array.

We can use the <iterator> field in the body of our foreach loop in the same way as we used the loop variable in the body of the for loop.

As we can see, we don't need to manage the array index when we use the foreach loop. As a result of this, we generally find that the foreach loop is easier to use than the for loop.

To demonstrate how we would use the foreach loop, let's rewrite the example from the section on for loops.

In this example, we created an array of 8 elements and then looped over each element in turn.

The code snippet below shows how we would implement this functionality with a foreach loop. We can also simulate this example on eda playground .

As we can see from this example, when we use a foreach loop we generally have to write less code to achieve the same result.

Multi Dimensional Arrays in SystemVerilog

So far, all of the arrays which we have discussed in this post have been one dimensional.

However, we can also create SystemVerilog arrays which have more than dimension. To do this, we simply add another field to the end of the array declaration.

The code snippet below shows the general syntax we would use to create a 2D array in SystemVerilog.

Both of the <elements> fields in this construct take the same form as the <element> field which we previously discussed in the section on static arrays.

As a result, we can either use a single number to determine the number of elements or we can specify a value for the low and high indexes. When we use the second approach, the <elements> field takes the form [high_index : low_index].

We can add as many <element> fields as needed to create a multidimensional array. For example, if we need a 3D array, then we would use a total of 3 <element> fields in our declaration.

In order to better demonstrate how we use multidimensional arrays in SystemVerilog, let's consider a basic example.

For this example, let's say that we want to create an array which has 2 elements both of which contain 4 8-bit wide logic types.

To do this, we simply need to add an extra field to the end of our normal array declaration. The code snippet below shows how we would do this.

• Assigning Data to Multidimensional Arrays

We use the same method to assign a multidimensional array as we would for a 1D array. However, we now use a pair of square brackets to define the element in both dimensions of the array.

As an example, suppose we want to assign the value of AAh to the the last element in both dimensions of the example array we declared in the previous section. The SystemVerilog code below shows how we would do this.

We can also use arrays literals to assign data to multidimensional arrays in SystemVerilog.

However, we now have to create a literal which itself contains a separate array literal for each dimension of the array.

For example, if we have a 2D array then we would create an array literal which is made up of 2 further array literals.

As an example, let's consider the case where we want to populate both elements of the 2D array example we created in the previous section.

However, we want all elements of the first dimension to be set to 0xFF and all elements in the second dimension to be set to 0.

The code snippet below shows how we would create an array literal to populate the entire 2D array with the required data. This code can also be simulated on eda playground .

• Packed and Unpacked Arrays in SystemVerilog

In all of the examples which we have considered so far, we have used unpacked arrays.

This means that each of the elements in the array is stored in a different memory location during simulation.

For example, suppose we have an array which consists of 4 8-bit elements. The code snippet below shows how we would create this is SystemVerilog.

As most simulators use 32 bit wide memory locations, we would end up with the memory contents shown below during simulation.

As we can see from this example, unpacked arrays can result in inefficient usage of memory as parts of the memory are unused.

In SystemVerilog, we can also use packed arrays to store our data in. Packed arrays will result in more efficient usage of memory when we run our simulations in some instances.

In contrast to unpacked arrays, all elements of a packed array are stored continuously in memory. This means that more than one element can be stored in a single memory location.

The code snippet below shows the general sytnax we use to declare a packed array in SystemVerilog.

All of the fields in the packed array declaration are the same as in the unpacked declaration. In fact, the only difference is that the <elements> field now comes before the <variable_name> field rather than after it.

To demonstrate how packed arrays are different to unpacked arrays, let's consider a simple example.

For this example, we will again create an array of 4 8-bit elements. However, this time we will declare the array as a packed type array.

The SystemVerilog code below shows would we declare this packed array.

This example would result in the memory allocation shown below.

We can see from this that the packed array has used a single 32-bit wide memory location to store the entire contents of the array.

In comparison to the unpacked array example, we can see how the packed array uses less memory by packing all of the data into a single memory location in this instance.

What is the difference between static arrays and dynamic arrays in SystemVerilog?

Static arrays have a fixed number of elements which are determined at compile time. In contrast, dynamic arrays don't have a fixed sized and we can add or remove elements during simulation.

Write the code to create an array which consists of 4 8-bit elements. Use an array literal to assign all of the elements in the array to 0.

Write a foreach loop for the array which you created in the last exercise

Write the code to declare a 2D array of int types. The array should have 2 elements in the first dimension and 8 elements in the second dimension.

What is the difference between an unpacked array and a packed array?

Each element of an unpacked array is stored in an individual memory address. In contrast, packed arrays are stored continuously in memory meaning that several elements can be stored in a single memory address.

2 comments on “An Introduction to SystemVerilog Arrays”

logic [7:0] [3:0] example; will give 8 nibbles

I think you need logic [3:0] [7:0] example; for your example

Thanks for pointing out the typo, I have now corrected it.

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SystemVerilog Arrays

Types of an array, fixed-size array in systemverilog, single dimensional array, array assignment, multidimensional array, two-dimensional array, three-dimensional array, scalar vs vector, packed and unpacked array, packed array, unpacked array, combination of a packed and unpacked array.

Mastering SystemVerilog Arrays: A Comprehensive Guide

Niranjana R

December 27, 2023

Table of Contents

Introduction

Welcome to “Mastering SystemVerilog Arrays: A Comprehensive Guide.” In the realm of hardware design and verification, SystemVerilog stands out as a powerful language, and understanding its array of capabilities is crucial for harnessing its full potential. Arrays in SystemVerilog offer a versatile and efficient way to manage data, making them a fundamental aspect of hardware description and verification languages.

A. Brief Overview of SystemVerilog

SystemVerilog, an extension of Verilog, was developed to address the challenges of modern hardware design and verification. It encompasses features that facilitate concise and readable code, making it a preferred language in the semiconductor industry. The language not only supports traditional hardware description but also incorporates powerful constructs for verification, making it an ideal choice for verification engineers.

B. Importance of Arrays in SystemVerilog

Arrays serve as a cornerstone in SystemVerilog programming, offering a structured and efficient means of handling data. Whether dealing with large datasets, complex algorithms, or dynamic data structures, arrays provide the flexibility needed to navigate the intricacies of hardware design and verification. This guide aims to unravel the intricacies of SystemVerilog arrays, from their basic definitions to advanced usage scenarios.

Now, let’s delve into the fundamental concepts of SystemVerilog arrays, exploring their declaration, initialization, and basic operations.

SystemVerilog Array Basics

A. definition and declaration of arrays.

In SystemVerilog, arrays are variables that can store multiple values of the same data type. Before delving into their usage, it’s essential to understand how to declare them. The syntax for declaring an array involves specifying the data type, array name, and size.

1. Syntax for Array Declaration

2. Data Types Supported for Arrays

SystemVerilog supports a variety of data types for arrays, including built-in types like bit, logic, and user-defined types. This flexibility allows for the creation of arrays tailored to specific design requirements.

B. Initialization of Arrays

Once declared, arrays can be initialized either explicitly or implicitly. Explicit initialization involves specifying values during declaration, while implicit initialization relies on default values.

1. Explicit Initialization

2. Implicit Initialization

Implicit initialization initializes all elements to their default values based on the data type.

Understanding these basic concepts sets the foundation for further exploration into array indexing, slicing, and the dynamic aspects of arrays in SystemVerilog, which we’ll delve into in the next section.

Array Indexing and Slicing

A. understanding array indexing.

Array elements in SystemVerilog are accessed using indices, and it’s crucial to grasp the indexing conventions. SystemVerilog uses zero-based indexing, meaning the first element of an array has an index of 0. For multi-dimensional arrays, indices are specified for each dimension.

1. Zero-Based Indexing

2. Multi-Dimensional Arrays

B. Slicing Techniques

Array slicing allows the extraction of a subset of elements from an array. This can be particularly useful when working with large datasets or when specific portions of an array need to be manipulated.

1. Basic Slicing

2. Advanced Slicing for Multidimensional Arrays

Understanding array indexing and slicing lays the groundwork for exploring dynamic arrays and associative arrays, which offer even greater flexibility in handling data in SystemVerilog. In the following sections, we’ll delve into these advanced array types and their applications.

Dynamic Arrays in SystemVerilog

A. introduction to dynamic arrays.

Dynamic arrays in SystemVerilog provide a flexible alternative to fixed-size arrays. Unlike static arrays, dynamic arrays don’t require a predefined size during declaration, allowing for dynamic allocation and resizing during runtime.

B. Dynamic Array Methods and Functions

1. Using the “new” Keyword

The new keyword is employed to dynamically allocate memory for a dynamic array. This enables the creation of arrays without specifying a fixed size at compile time.

2. Resizing Arrays

Dynamic arrays can be resized during runtime using the $resize system task. This task allows the array to grow or shrink as needed.

Understanding the dynamics of dynamic arrays opens the door to more adaptive data structures in SystemVerilog. However, when it comes to associative arrays, SystemVerilog offers a unique and powerful tool for handling complex data relationships.

Associative Arrays in SystemVerilog

A. definition and purpose of associative arrays.

Associative arrays, also known as “hash” or “unordered” arrays, differ from traditional arrays in that they use keys instead of indices to access elements. This makes them particularly useful for scenarios where the relationship between data points is not strictly sequential.

B. Operations on Associative Arrays

1. Adding and Removing Elements

2. Iterating Through Associative Arrays

As we explore associative arrays, we’ll uncover their usefulness in various applications, from handling configuration data to efficiently managing complex data relationships in verification environments.

In the upcoming sections, we’ll delve into practical array manipulation techniques, including sorting and searching arrays, and showcase real-world examples of SystemVerilog array usage. Understanding these advanced topics will empower you to leverage arrays effectively in your hardware design and verification projects.

SystemVerilog Array Manipulation

A. sorting arrays.

1. Using Built-in Sorting Functions

SystemVerilog provides convenient built-in functions for sorting arrays. The $sort function simplifies the process of arranging elements in ascending or descending order.

2. Implementing Custom Sorting Algorithms

For more complex sorting requirements, custom sorting algorithms can be implemented. Understanding algorithms like quicksort or mergesort allows for tailored solutions.

B. Searching Arrays

1. Linear Search

Linear search is a straightforward method for finding an element in an array. It involves traversing the array sequentially until the target element is located.

2. Binary Search

Binary search is a more efficient search algorithm but requires a sorted array. It involves repeatedly dividing the search range in half until the target is found.

Mastering array manipulation techniques like sorting and searching is crucial for optimizing performance in hardware design and verification scenarios. In the next section, we’ll explore real-world examples of SystemVerilog array usage, demonstrating how these techniques can be applied in practical situations.

Array Usage in Real-world Examples

A. case studies.

1. Verifying Complex Hardware Designs

In the realm of hardware verification, arrays play a pivotal role in managing test vectors, tracking signals, and validating circuit behavior. Consider a scenario where an intricate hardware design involves multiple registers with varying configurations. An array can efficiently store and manipulate these configurations, simplifying the verification process.

2. Handling Testbench Data with Arrays

In a testbench environment, arrays can be instrumental in managing stimulus data, response checking, and coverage tracking. Consider a testbench scenario where different test cases are generated and executed. Arrays can store the test cases and their corresponding expected outcomes, facilitating efficient testbench automation.

By examining these case studies, it becomes evident how SystemVerilog arrays can streamline complex processes in hardware design and verification.

In this comprehensive guide, we have embarked on a journey to master SystemVerilog arrays, unraveling their intricacies and exploring their myriad applications in hardware design and verification. From the fundamental concepts of array declaration, initialization, and indexing to advanced topics like dynamic arrays and associative arrays, we’ve covered the spectrum of array-related features that SystemVerilog offers.

Understanding the power of SystemVerilog arrays is crucial for harnessing the language’s capabilities in handling diverse data structures, managing complex hardware designs, and creating efficient testbenches. The ability to manipulate arrays through sorting, searching, and dynamic allocation provides engineers with the tools needed to optimize performance and streamline their coding practices.

The real-world case studies showcased the practical application of SystemVerilog arrays in scenarios ranging from complex hardware designs with multiple configurations to automated testbenches handling diverse test cases. These examples highlight how arrays can enhance readability, maintainability, and efficiency in real-world projects.

As we conclude this guide, it is essential to emphasize the significance of best practices in SystemVerilog array usage. By optimizing performance, writing readable and maintainable code, and handling large data sets with efficiency, engineers can ensure that their array-based implementations contribute to robust and reliable hardware designs.

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1 thought on “Mastering SystemVerilog Arrays: A Comprehensive Guide”

What fundamental concepts of SystemVerilog arrays does the article aim to explore, including aspects such as declaration, initialization, and basic operations? regard Telkom University

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Verilog Arrays Plain and Simple

Arrays are an integral part of many modern programming languages. Verilog arrays are quite simple; the Verilog-2005 standard has only 2 pages describing arrays, a stark contrast from SystemVerilog-2012 which has 20+ pages on arrays. Having a good understanding of what array features are available in plain Verilog will help understand the motivation and improvements introduced in SystemVerilog. In this article I will restrict the discussion to plain Verilog arrays, and discuss SystemVerilog arrays in an upcoming post.

Verilog Arrays

Verilog arrays can be used to group elements into multidimensional objects to be manipulated more easily. Since Verilog does not have user-defined types, we are restricted to arrays of built-in Verilog types like nets, regs, and other Verilog variable types.

Each array dimension is declared by having the min and max indices in square brackets. Array indices can be written in either direction:

Personally I prefer the array2 form for consistency, since I also write vector indices (square brackets before the array name) in [most_significant:least_significant] form. However, this is only a preference not a requirement.

A multi-dimensional array can be declared by having multiple dimensions after the array declaration. Any square brackets before the array identifier is part of the data type that is being replicated in the array.

The Verilog-2005 specification also calls a one-dimensional array with elements of type reg a memory . It is useful for modeling memory elements like read-only memory (ROM), and random access memory (RAM).

Verilog arrays are synthesizable, so you can use them in synthesizable RTL code.

Assigning and Copying Verilog Arrays

Verilog arrays can only be referenced one element at a time. Therefore, an array has to be copied a single element at a time. Array initialization has to happen a single element at a time. It is possible, however, to loop through array elements with a generate or similar loop construct. Elements of a memory must also be referenced one element at a time.

Verilog arrays are plain, simple, but quite limited. They really do not have many features beyond the basics of grouping signals together into a multidimensional structure. SystemVerilog arrays, on the other hand, are much more flexible and have a wide range of new features and uses. In the next article— SystemVerilog arrays, Synthesizable and Flexible —I will discuss the new features that have been added to SystemVerilog arrays and how to use them.

• 1364-2005 – IEEE Standard for Verilog Hardware Description Language

Sample Source Code

The accompany source code for this article is a toy example module and testbench that illustrates SystemVerilog array capabilities, including using an array as a port, assigning multi-dimensional arrays, and assigning slices of arrays. Download and run it to see how it works!

[lab_subscriber_download_form download_id=11].

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14 thoughts on “Verilog Arrays Plain and Simple”

In the initial array_name example, don’t you have the msb and lsb swapped around?

Hi Graham. You’re right! I’ve fixed the typo. Thanks for noticing the error.

what to do if i want to copy an array content to other array? Is using a loop the only way to do so ?

Hi Priyansh. With plain Verilog-2005, yes that is the only way to do it. With SystemVerilog you can manipulate arrays much more easily, like copying slices, dimensions, entire arrays. See my post SystemVerilog Arrays, Flexible and Synthesizable .

If there’s no difference between array1[0:7] and array2[7:0], why does one have to put the lsb and msb?

Hi Stefan. I think internally depending on which way you define the array, it does potentially affect the location of where the data is placed (e.g. where array1[0] is located). But that will be transparent you when coding RTL as long as you use the indices consistently. SystemVerilog actually allows you to define an array with just array1[SIZE], which is the same as array1[0:SIZE-1].

I have a doubt regarding 2D arrays in Verilog. Suppose I want a design which take two 2D arrays as inputs and gives an output as 2D array. When I tried to declare the input output ports as 2D arrays, it did not work at all. I request you to kindly suggest me the way i can do my above said task in verilog.

Thanks in Advance…..

Hi. See an example I created on edaplayground here .

Hi Jason, I want to instantiate FIFO block 256 times. How to write an array?

Thanks In Advance

Hi Chetana. If you want to instantiate a module multiple times in an array, you need to use a generate loop. See my article Verilog Generate Configurable Designs .

Hi sir..how can i form covariance matrix in verilog.sir please suggest coding.

Hi Jason, I have a question regarding arrays and memory. I want to write the content of a 1D array into a specific location of a memory. But I’m not able to do this for some reason. I request you to kindly suggest me the way i can do my above said task in verilog.

Thanks in Advance…

Hi Gautham. Sorry I don’t fully understand your question. A 1D array has multiple elements. How can you write that into one location of a memory? Or you mean you want to write it to multiple consecutive locations of the memory?

Hi Jason. Thank you for replying back. I’m sorry that the question is not very clear. Yes, I wanted to ask how to write data from a 1D array into consecutive locations of a memory in verilog.

Thank you…

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Apostrophe in Verilog array assignment

I've seen a Verilog example that assigns values to an array as follows :

What's the purpose of the apostrophe (') ? How will this be any different ?

• system-verilog

SystemVerilog has the array assignment operator '{...} in addition to the concatenation operator {...} .

Concatentation is for packed arrays - basically you combine multiple signals into a single bus.

You can nest concatenation operators too. The following assigns the same value to b as was assigned to a in the previous example. Nested concatenations flatten out to a single bus.

Array assignment is for unpacked arrays:

Arrays can also be multi-dimensional, in which case you can initialise each dimension (from right to left) by nesting array assignments:

You can also combine the two (concatentation and array assignment):

On to your two examples.

The first example is of array initialisation. This would assign array[0][0] = 0 , array[1][0] = 1 and so on, e.g. array[0][1] = 4 and array[3][2] = 11 . For example, it could be used to initialise an unpacked array, such as:

In the second example, you are concatenating twelve 32-bit numbers (*) together, which would result in a single 384 bit number. This could be assigned to a packed array, but not an unpacked array:

(*) Note, these are technically unsized literals, so the concatenation is not strictly legal, though most synthesis tools will treat them as 32-bit values and allow the concatentation (possibly with warnings). Always use size specifiers on your literals when performing concatenation.

• 1 \$\begingroup\$ Just a note: the statement wire [383:0] array = {{0,1,2,3},{4,5,6,7},{8,9,10,11}}; is illegal according to the LRM. You are not allowed to have a packed array concatenation with unsized literals. Some tools allow this to pass through with a warning but you're really setting yourself up for trouble if you write {v1,0,v2} exepecting a single digit 0 in between v1 and v2 ` \$\endgroup\$ –  dave_59 Commented Sep 6, 2020 at 17:39
• 1 \$\begingroup\$ @dave_59 most things will interpret the size as 32-bit, but yes, I totally agree that the using unsized literals is a recipe for pain and not guaranteed to work. I've added a note. \$\endgroup\$ –  Tom Carpenter Commented Sep 6, 2020 at 17:59

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How to define and assign Verilog 2d Arrays

I'm trying to create a two dimensional array in that form:

and when I try to assign a value to it lets say

it gives some errors saying that:

"Reference to scalar reg array 'arr' is not a legal net lvalue" and "Illegal left hand side of continuous assign".

So my intention is to assign a number in the index of the array. How does this assignment work? Any help, suggestion would be highly appreciated.

2 Answers 2

First of all, you can't assign to regs. assigns drive wire types, not reg types. To drive a reg type you need a statement inside a logic block like an always block.

Secondly, based on what you've written, I think you're looking for an array of multi-bit elements, not a 2d array.

reg arr[5:0][0:5]; Defines a 2D array of single bits. If you want an array of multi-bit values that can hold larger than a bit, you declare it like this:

reg [M:0] arr[0:N] - This describes an array of (N+1) elements, where each element is a M+1 bit number. If you declare it in this fashion, then you should be able to store a value like 22 into it, assuming you use an always block.

• Yeah that is exactly what I am looking for. What about storing values, is it a must to use an always block can't we just store them manually? And more thing, should we use assign then? –  bledi Commented Apr 16, 2013 at 19:37
• What do you mean 'manually'? You can use an initial block if you just want to assign it at start of time. assigns are for driving wires only, not regs. Check out any introductory verilog tutorial for more info on the difference between reg and wire. –  Tim Commented Apr 16, 2013 at 19:40
• 9 (M+1) , (N+1) , not -1 –  EML Commented Apr 17, 2013 at 9:48

You can not use a continuous assignment (aka an assign statement) on a reg type. This has nothing to do with it being an array.

Changing the declaration of arr to be of type wire will get you past the error message you posted. Or, you can assign it using a procedural assignment in an initial or always block.

However you still need to provide both dimensions of the array in the assignment. You are declaring a 2d array of 1-bit values.

So you would need to specify it as:

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SystemVerilog Unpacked Arrays

An unpacked array is used to refer to dimensions declared after the variable name.

Unpacked arrays may be fixed-size arrays, dynamic arrays , associative arrays or queues .

Single Dimensional Unpacked Array

Multidimensional unpacked array, packed + unpacked array.

The example shown below illustrates a multidimensional packed + unpacked array.

In a multidimensional declaration, the dimensions declared before the name vary more faster than the dimensions following the name.

Verification Guide

• Fixed Size Arrays
• Packed and Un-Packed Arrays
• Dynamic Array
• Associative Array

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